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Mentor Graphics Extends Co-Verification Support for the Motorola PowerPC Architecture
WILSONVILLE, Ore.--(BUSINESS WIRE)--May 22, 2001--Mentor Graphics
Corp. (Nasdaq:MENT), the world's leading provider of hardware/software
co-verification solutions, today announced the availability of new
co-verification Processor Support Packages (PSPs) for members of the
Motorola PowerPC(TM) family.
Developed for use with the Mentor Graphics® Seamless®
Co-Verification Environment(TM) (CVE(TM)), the PSPs accelerate design
schedules by enabling designers to validate hardware and software
interfaces in virtual prototype early in the design process, avoiding
time-consuming design re-spins and shortening time-to-market.
The PSPs will support the Motorola MPC8240 Integrated PowerPC
Processor and MPC755 PowerPC embedded microprocessors: two premier
processors used in networking and telecommunications applications such
as routers, switches, network storage applications and image display
systems.
``With first-pass success a necessity in the fast-paced
telecommunications and networking markets, co-verification has become
an integral part of the embedded system design flow,'' said Brian
Wilkie, corporate vice president and general manager for Motorola's
Computing Platform Division. ``Mentor Graphics has been a long-standing
and valued partner, providing comprehensive co-verification support
for the PowerQUICC and PowerPC families.''
By combining a high-speed PowerPC embedded processor along with
unparalleled integration of networking and communications peripherals,
Motorola provides customers with an innovative, total-system solution
for building high-end communications systems. The MPC8240 is based on
the successful PowerPC 603e embedded processor core, and integrates
independent execution units targeted at the communications market. The
combination of the PowerPC cores and the independent execution units
reduces chip counts and power consumption and simplifies board design
for customers developing embedded systems for such applications as
networking and telecommunications.
To accelerate the development process of the PSPs, Mentor Graphics
used existing simulation models from Motorola. This reuse methodology
helps to ensure that customers have rapid access to the processor
models in lock-step with new processor releases, such as model
follow-on parts, like the MPC8245.
``Together Motorola and Mentor Graphics have worked to ensure that
co-verification models are available in conjunction with new Motorola
processor releases,'' said Serge Leef, general manager, System-on-Chip
Verification Division, Mentor Graphics. ``Early access to
co-verification models allows time-constrained networking and
telecommunications designers to merge the hardware and software worlds
earlier in the design process, shortening the overall development
cycle.''
Availability and Pricing
The Motorola MPC755 PowerPC PSP is available now starting at
$30,000. The MPC8240 Integrated PowerPC PSP will be available in
September 2001 with pricing also starting at $30,000. Mentor Graphics
also provides PSPs for other Motorola microprocessors including the
MPC603e, MPC740/750, MPC7400, MPC860 and MPC8260. For additional
information about Seamless or to register for upcoming Seamless
workshops and seminars, visit the Seamless web site at
www.mentor.com/seamless.
About MPC8240 and MPC755
The MPC8240 Integrated PowerPC Processor provides a high level of
integration, reducing chip count from five discrete chips to one,
thereby significantly reducing system component cost for applications
where space, power consumption and performance are critical
requirements. This general-purpose integrated processor targets
systems using PCI interfaces in networking infrastructure,
telecommunications, and other embedded markets.
MPC755 PowerPC microprocessors are high-performance, low-power,
32-bit implementations of the PowerPC Reduced Instruction Set Computer
(RISC) architecture, specially enhanced for embedded applications.
MPC755 PowerPC microprocessors are also drop-in replacements for the
award-winning PowerPC 750(TM).
About Seamless
Combining the best in embedded software development tools with
logic simulation, the Mentor Graphics Seamless co-verification
environment delivers high performance co-verification months before a
hardware prototype can be built. The Seamless environment enables
software and hardware development to be parallel removing the software
from the critical path, and reducing the risk of hardware prototype
iterations resulting from integration errors. User-controlled
optimizations boost performance by isolating the logic simulator from
software-intensive operations such as block memory transfers and
algorithmic routines.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products
and consulting services for the world's most successful electronics
and semiconductor companies. Established in 1981, the company reported
revenues over the last 12 months of more than $600 million and employs
approximately 2,850 people worldwide. Corporate headquarters are
located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777;
Silicon Valley headquarters are located at 1001 Ridder Park Drive, San
Jose, California 95131-2314. World Wide Web site: www.mentor.com.
Mentor Graphics and Seamless are registered trademarks of Mentor
Graphics Corporation. Co-Verification Environment and CVE are
trademarks of Mentor Graphics Corporation. PowerPC and PowerQUICC are
trademarks of Motorola. All other company or product names are the
registered trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics
Wendy Slocum, 503/685-1145
wendy_slocum@mentor.com
or
Benjamin Group/BSMG Worldwide
Victor Domine, 408/559-6090
victor_domine@benjamingroup.com
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